Traffic signal control system

ABSTRACT

An apparatus for centrally controlling traffic over a wide geographical area. A master controller collects traffic information from traffic signal stations throughout the area at predetermined intervals, and stores this information in its associated memory, along with various operating time parameters associated with the traffic signal operation at each traffic signal station. A central processor reads and evaluates the traffic information stored in the master controller and continuously updates the operating time parameters. The master controller controls the traffic signals on the basis of their operating time parameters.

United States Patent [191 Kato et al.

[54] TRAFFIC SIGNAL CONTROL SYSTEM [75] Inventors: Toshio Kato; TatsuroIchihara,

both of Kyoto,,lapan [73] Assignee: Omron Tateisi Electronics Co.,

Kyoto, Japan [22] Filed: Mar. 25, 1971 [21] Appl. No.: 128,037

[451 June 5, 1973 3,528,054 9/1970 Auer et al ..340/35 PrimaryExaminerWilliam C. Cooper AttorneyChristensen & Sanborn [57] ABSTRACT Anapparatus for centrally controlling traffic over a wide geographicalarea. A master controller collects traffic information from trafficsignal stations throughout the area at predetermined intervals, andstores this information in its associated memory, along with variousoperating time parameters associated with the traffic signal operationat each traffic signal station. A central processor reads and evaluatesthe traffic information stored in the master controller and continuouslyupdates the operating time parameters. The master controller controlsthe traffic signals on the basis of their operating time parameters.

3 Claims, 5 Drawing Figures TRAFFIC SIGNAL CONTROL SYSTEM This inventionrelates to a traffic control system and, more particularly, to a systemfor centrally controlling traffic in a wide area.

There are known many types of systems for centrally controlling trafficin a wide area. Generally, such a system comprises a plurality ofterminal or local stations provided at different spots over the widearea where traffic is to be controlled and a central station whichcentrally controls those local stations. The central station collectsvarious data concerning traffic from the local stations and analyzesthem to foretell and indicate the degree of traffic congestion anddetermines what control pattern is to be selected by each of the localstations.

The central station is provided with a processing unit including anelectronic computer which performs various required operations. In theprior art the electronic computer samples various traffic informationdetected by the local stations, that is, the presence or absence ofvehicles at each of the spots and the time during which any vehicleexists within the detection area, and calculates the traffic volume ateach of the spots, time occupancy, the average vehicle speed, etc. fromthe sampled information. In addition to these operations, the

computer must perform necessary calculations to select the controlpattern in accordance with which the traffic signal at each of the spotsis to be controlled and to provide signals to change the traffic signalsin accordance with the selected pattern, and perform various otheroperations such as recording or indication'of necessary traffic data.Therefore, in order to effect smooth and efficient traffic control, thecomputer must have a large capacity and be capable of high-speedoperation.

Accordingly, the primary object of the invention is to provide a trafficcontrol system which includes a central station provided with aprocessing unit capable of operation with a computer having a relativelysmall capacity.

Another object of the invention is to provide such a traffic controlsystem as aforesaid, wherein the central processing unit itself does notcollect the traffic information detected at various spots, which iscollected by and-stored in a separate master controller, so that thecentral processing unit samples the data stored in the master controllerevery predetermined period of time and processes them to providerequired data to be used for control purposes.

Another object of the invention is provide such a traffic control systemas aforesaid, wherein when the function of the central processing unithas become paralyzedfor one cause or another, the traffic signals atthe-different spots are controlled on the basis of the trafficinformation stored in the master controller at that time.

The invention will become more apparent from the following descriptionof a preferred embodiment thereof with reference to the accompanyingdrawings, therein; A

FIG. 1 is a block diagram of one embodiment of the invention;

FIGS. 2 and 3 are block diagrams of portions of the master controllerprovided in the central station;

FIG. 4 is a detailed block diagram of the input-output (I/O) deviceprovided in the central station; and

FIG. 5 is a block diagram of another portion of the master controller.

Referring now to FIG. 1, there is shown a road network comprising aplurality of roads R, with traffic signals installed at different spotswhere traffic flow is to be controlled. Local or terminal stations 11 tol-n are provided each to control one of the traffic signals. The trafficinformation detected by each local station is generally transmitted to acentral station by means of telephone circuits. The central stationincludes a MODEM 2, a detected traffic information collector 3, a mastercontroller 4, a U0 device 5, a processing unit 6 and a control signaltransmitter 7. The traffic information transmitted every moment fromeach local station is received by the MODEM 2 and collected by thecollector 3 and then applied to the master controller 4 to be storedtherein. The information or data stored in the master controller 4 areapplied to the processing unit 6 every predetermined period of timeunder the control of the I/O device 5.

Thus, the processing unit 6 does not collect the data to be processed.Instead, upon passage of every predetermined unit period of time theunit 6 calls the master controller 4 to receive the data therefrom andperforms necessary operation on the data. This means that the unit 6need not always be operating and that at a high speed.

The master controller 4 stores various data for each local station, suchas the time of each step of the traffic signals, offset and split (thesewill be referred to as the operating time data) and the time that haselapsed since the reference time (the elapsed time) and the steps (thesewill be referred to as the variable data). When the processing unit hasprocessed the detected traffic information, on the basis of the resultof the processing the operating time data stored in the mastercontroller are changed so as to be most suitable for control of trafficabout the spot at which the traffic information has been detected, andthe master controller 4 controls each local station so that the latterin turn controls its traffic signals in accordance with the data thusprovided. The data are transmitted by the device 7 to the local stations1-1 to l-n via the MODEM 2.

As will be apparent from the above description, the master controller 4is operatively connected to the processing unit 6 through the I/O device5. Most of the operations required for control of the traffic signalsare performed by the master controller 4, so that the computer in theprocessing unit 6 may be of a relatively small capacity and have arelatively low operating speed. Since the master controller 4 stores thefixed data, if the processing unit 6 has made an error or its functionhas become paralyzed, the operating time data stored in the mastercontroller 4 can be used for coordinated or fixed cycle control of thetraffic signals as fail-safe operation of the system.

Now turning to FIGS. 2 and 3, the master controller 4 will be describedin detail. FIG. 2 schematically shows that part of the master controllerwhich controls the local stations on the basis of the fixed data. Amemory device comprising core memories stores the fixed data, thevariable data and instruction data. A timing pulse generator 200produces timing pulses to be applied to a controller 300, whichtransfers the pulses to the variable data stored in the memory device.As the pulses are added to the data, they are changed. The changed dataare collated with the operating time data for comparison. Every time anagreement occurs between the changing variable data and the fixed data,

a signal is produced to control the terminal stations 1-l to 1n. Thus,each of the traffic signals is changed in accordance with the operatingtime data stored in the memory device 100. It has already been mentionedthat the fixed data are always being changed on the basis of the resultof the operation of the processing unit 6. This means that the operatingtime data are always determined on the basis of the latest detectedtraffic information, so that the traffic signals are always controiledon the basis of the newest operating time data. In other words, each ofthe traffic signals is controlled in a manner most suitable for thepresent traffic condition at each spot.

In case the master controller 4 is controlling the traffic signal at aselected one of the spots so that the signal is changed at a fixedcycle, the pulse generator 200 produces one timing pulse per second tobe applied to the controller 300, whereupon the controller 300 reads thedata expressing the time that has elapsed since the reference time (thatis, the time at which the step began) as stored in the memory device100, and l is added to the data, which are again written in the memorydevice 100. This means that the data concerning the elapsed time haveone second added thereto upon lapse of every 1 second. At the same time,the data concerning the step stored in the device 100 are read by thecontroller 300, and on the basis 'of that data the data concerning theduration time of the step at that time are read from the operating timedata in the memory device 100. The data are compared with the dataexpressing the time that has elapsed since the reference time. When bothdata have come to agree, the time set for that step has now passed.Then, the elapsed time stored in the memory device is reset, and thedata expressing that step are read by the controller 300 so that 1" isadded to the data, and the new data are written in the memory device 100as the data concerning the next step. At the same time, a control signalis applied to the terminal station so as to change the step of trafficsignal to the next one.

' Suppose that the master controller 4 is conducting traffic-actuatedcontrol of the traffic signals. In this case, whenever the pulsegenerator 200 produces a clock pulse, the data expressing the time thathas elapsed since the reference time are read by the controller 300 fromthe memory device 100, and l is added to the data, which are thenwritten in the memory 100. On the other hand, the data expressing thestep are read by the controller 300, and on the basis of the data thedata concerning the initial green time at that step is read from thememory device 100, and is compared with the data concerning the timethat has elapsed since the reference time. When the data conceming thetime that has elapsed since the reference time exceeds the dataconcerning the initial green time, the manner in which the trafficsignal is controlled will depends on whether or not there is any vehicleon the spot. If there is no vehicle on the spot, a signal is applied tothe corresponding terminal station to change from the present step tothe next one, that is, the traffic signal is changed to yellowimmediately upon lapse of the initial green time. On the contrary, ifthere is any vehicle on the spot, the green time is extended and thecontroller 300 reads from the memory device 100 the data concerning thetime (the extension of the green time) that has passed since the end ofthe initial green time, and l is added to the read data, which are thenwritten in the memory device. The controller 300 reads from the memorydevice the data concerning the actual extension of the green time andthe data concerning the unit extension of the green time, so that thetwo data are compared. If the two data are equal, it is again checkedwhether there is any vehicle on the spot at that time. If there is novehicle there, a signal is applied to the terminal station to change thestep of the traffic signal to next one. However, if there is any vehicleon the spot, the green time is again extended so that the aboveoperation is repeated. As the green time is extended in this manner, thedata concerning the extension, that is, the time that has elapsed sincethe end of the initial green time and the data concerning the maximumextension of the green time are read by the controller 300 from thememory device 100 and compared. If the former data have come to exceedthe latter, the green time can no longer be extended, so that a signalis given to the corresponding terminal station to change the trafficsignal at the spot to the next step, say, red.

In case the traffic signals are controlled in a coordinated manner, thepulse generator 200 produces 100 pulse per signal cycle to be applied tothe controller 300. (The pulses will be referred to as the percentpulses.) Whenever one pulse is applied to the controller 300, one of thevariable data stored in the device 100, for example, the data concerningthe time that has passed since the reference time and which is expressedas a percent of one signal cycle, are read by the controller 300, and lis added to the data, which are then stored in the memory device 100. Onthe other hand, the operating time data concerning offset and split asstored in the memory device 100 are read by the controller 300 uponapplication of every one percent pulse thereto, so that these data arecompared with the previously mentioned data to which l is added uponapplication of every one percent pulse to the controller 300. If thedata expressing the time that has elapsed since the reference time hascome to exceed the data expressing the offset, a signal is applied tothe corresponding terminal or local station to start the green signal.If the above-mentioned data expressing the elapsed time has come toexceed the data expressing the split, a signal is applied to thecorresponding terminal station to terminate the green signal. Theoperating time data stored in the memory device 100 are determined bythe processing unit 6 on the basis of the traffic conditions detected ateach of the spots.

Turning now to FIG. 3 which shows that portion of the master controller4 which collects the traffic informations or data detected at thedifferent spots, a plurality of vehicle detectors 1'l to 1'-n areprovided at the spots where traffic is to be controlled. While each ofthe detectors is detecting a vehicle, it produces an output signal l,"which is transmitted through the MODEM 2 to the data collector 3. Thememory device 100 has storage areas corresponding to the detectors 1'-lto 1n, respectively. The pulse generator 200 produces a pulse everypredetermined period of time, say, every 50 m. see. This pulse signalcauses an address register MAR included in the controller 300 to scanthe coincidence circuits 310-1 to 310n within 50 m.sec. and at the sametime successively designate the addresses of the spots at which thedetectors are installed. Suppose that the register MAR has designatedthe coincidence circuit 310-1. When the vehicle detector 1'-1- hasdetected a vehicle, the coincidence circuit 3l0-1 produces an outputsignal, which is applied to an OR circuit 320. Therefore, when thecoincidence circuit 310-1 produces an output, the OR circuit 320produces an output. On the other hand, when the address register MAR hasdesignated the coincidence circuit 3111-1, the data concerning thecorresponding spot that are then stored in the memory device 100 areread therefrom. At this time, if there is an output from the coincidencecircuit 310, the output from the OR circuit 320 causes the controller300 to add 1 to that data, and the new data are again'written in thememory device 100.

In this manner, while the vehicle detector 1'1 is detecting a vehicle, lis added to the data in the corresponding address of the memory device100 every 50 m. sec. Therefore, if the data are sampled every unitperiod of time, the time occupancy for the unit period of time at thespot can be obtained. Every time sampling is done, the data at thecorresponding address in the memory device 100 are rewritten.

The traffic volume in the unit period of time at each of the spots canbe obtained in the following manner. When the coincidence circuit 310-1has been designated by the address resister MAR, the other correspondingaddress in the memory device 100 is designated. When a coincidencecircuit 120 produces an output, 1 is added to the data in that otheraddress, and the new data are written in the memory device. The data areread by the controller 300. If the data used to obtain theabove-mentioned time occupancy comprise 16 bits, the last three hits arestored in the register 110 through the controller 300. If the first ofthe four bits input to the coincidence circuit 120 is 1, the second bit0, the third bit and the fourth bit 0, the circuit 120 produces anoutput signal. This condition occurs when the detector has detected onevehicle. When the detector 1l is detecting a vehicle, the OR circuit 320produces an output signal every time the coincidence circuit 310-1 isdesignated. Therefore, while the detector is detecting a vehicle, thecoincidence circuit 120 produces an output when it has received thesecond of the pulses produced by the pulse generator 200 every 50 m.see. after it received the first one, and thereafter the circuit 120produces no output signal. Therefore, if the data stored in the addressof the memory device 100 are sampled every unit period of time, thetraffic volume per unit period of time at the corresponding spot can beobtained.

In the above manner, the traffic informations detected at the differentspots are collected and stored in the corresponding areas in the memorydevice 100 included in the master controller 4. The informations aresent to the processing unit 6 through the U0 device every unit period oftime. The operating time data stored in the memory device 100 of thecontroller 4 are rewritten on the basis of the result of operation ofthe processing unit 6. The detected data stored in the memory device 100are transfered to the processing unit 6 every unit period of time underthe control of the I/O device 5. The transferring operation will beexplained with reference to FIG. 4.

As shown in FIG. 4, the master controller 4, the I/O device 5 and theprocessing unit 6 are connected by means of data lines B1 to B4, andthere are also provided control lines Cl to"'C4. In case the operatingtime data processed by the processing unit 6 and temporarily stored inthe memory device of the unit are written as the operating time data inthe memory device of the master controller 4, and also in case the datadetected at the spots are written in the memory device of the processingunit 6, the processing unit 6 designates the first of the addresses inthe memory device of the processing unit 6, the first of the addressesin the memory device 100 of the master controller 4, the number of thewords to be transferred and the instruction word.

An FNR register 8 stores the above-mentioned instruction word; an IMRregister 9 stores the first address of the memory device 100 of themaster controller 4; and MAC register 10 stores the first address of thememory device of the processing unit 6; and a TNR register 11 stores thenumber of the words to be transferred. There are also shown in FIG. 4 aclock pulse generator 12, a translating circuit 13 which receives theoutput pulses from the generator 12 to control the gates and registersto be described hereinafter, a TWR register 14, an adder 15 and a BURregister 16.

In this embodiment, the transfer of data between the controller 4 andthe unit 6 is controlled by the asynchronous method that the transferoperation is interlocked by the request signal and the response signal.To put it in more details, when the clock pulse generator 12 produces apulse to be applied to the translating circuit 13, the circuit 13produces an output as the request signal, and after a response signalcorresponding to the request signal has been produced, the circuit 13receives the next clock pulse from the generator 12. In other words, thenext clock pulse is not applied to the circuit 13 until the requestsignal is produced, so that the present condition is maintained untilthe next clock pulse is produced.

The control lines Cl include a line SLFN, which becomes energized or onwhen a code for instructing the data to be transferred and a code fordesignating the I/O device 5 have been applied to the information lineBl, provided that there is no data transfer request signal from thedevices connected to the processing unit 6. The line SLEN becomesdeenergized or ofF when a line ACPT has become on.

The control lines C2 further includes a line SRVI. In case the data aretransferred from the master controller 4 to the processing unit 6, theline SRVI becomes on when the data to be transferred have been appliedto the data line B1, and off when a line SRVO included in the controlline Cl has become on." In case the data are transferred from theprocessing unit 6 to the master controller 4, the line SRVI becomes onwhen the I/O device 5 has become ready to receive data, and of when theline SRVO has become on upon complection of transfer of the data.

In case the data are transferred from the master controller 4 to theprocessing unit 6, the line SRVO becomes on after the processing unit 6has received the data on the data line B1, and of when the line SRVI ofthe control lines C2 has become off. In case the data are transferredfrom the processing unit 6 to the master controller 4, the line SRVObecomes on when the line Bl has received the data to be transferred, andoff when the control line SRVI has become off.

The control lines C2 further include a line ADRI. In case the data aretransferred from the master controller 4 to the processing unit 6, theline ADRI becomes on" when the [/0 device 5 has applied to the data lineB1 the data concerning the address in the core memory of the processingunit 6 to which the data are to be transferred, and of when the lineSRVO in the control lines Cl has become on.

The line REQD included in the control lines C2 becomes on when the Udevice has got ready to transfer one word of the data, and off when theline ACK included in the control lines C1 and then the line INTLincluded in the control lines C2 have become (on-1,

The line REQI included in the control lines C2 becomes on when the U0device 5, or one of the other devices connected to the processing unit 6has made a request for data transfer, and off when the line ACPT in thecontrol lines becomes on after the line ACK in the control lines C1became on. The line ACK becomes of when either the line REQD or REQI hasbecome on, with the lines ACPT, INTL and DRCT being off. The line INTLincluded in the control lines C2 becomes on when the I/O device 5 hasreceived the signal on the line ACK, and off when the data transfer hasbeen completed so that the line SRVO of the control lines C1 has becomeoff.

The line MARC of the control lines C3 becomes on when the addressregister MAR of the master controller 4 is set; the line RWCL becomes onwhen the memory device 100 is energized; the line RWGL becomes on whendata are written into the memory device 100; and the line MBRG becomeson to set the memory register when the data in the memory device 100 areread.

The transfer of data between the master controller 4 and the [/0 device5 is performed so that every one word is transferred at one time. Whentransfer of one word has been finished, the control line ONEE becomeson, and when transfer of all the data has been completed, the line ALLEbecomes on.

The line UERR included in the control lines C3 becomes on when thefunction of the processing unit has become paralyzed. When the mastercontroller 4 receives the signal on the line UERR, it controls theterminal stations so that a coordinated traffic signal control iseffected in accordance with the operating time data stored in the memorydevice 100.

The signals on the above-mentioned control lines CI C4 are used as theresponse or confirmation signals in the transfer of data between theprocessing unit 6 and the I/O device 5 and also between the mastercontroller 4 and the device 5.

When the first clock pulse has been produced by the pulse generator 12,if the request signal lines ACPT, INTL and DRCT are off, the first gatecircuit 17 receives the signal from the translating circuit 13 so as tobe opened. After that, when the response signal line SLFN becomes on,the FNR register 8 is set, so that the instruction code and the datadesignating the U0 device 5 on the line B1 are stored in the FNRregister 8, and then a second clock pulse is applied to the translatingcircuit 13.

When the second clock pulse has been produced, if the request signalline ACPT is on and the response signal line SLFN is off, a third clockpulse is applied to the translating circuit 13. When the third clockpulse has been produced, if there is a request signal on the line SRVI,the first gate 17 is opened. After that, when the response signal lineSRVO becomes on, the MAC register is set, so that the data on the lineB1 is stored in the MAC register 10, and a fourth clock pulse is appliedto the translating circuit 13. After the fourth clock pulse wasproduced, when the response signal line SRVO has become off, the requestsignal line ACPT also becomes of and a fifth clock pulse is applied tothe translating circuit 13. When the fifth clock pulse has beenproduced, the TWR register 14 is reset by the signal received from thetranslating circuit 13, and at the same time a request signal isproduced on the line REQD. After that, when the response signal line ACKbecomes on, a sixth clock pulse is applied to the translating circuit13, whereupon the request signal line INTL becomes on. After that, whenthe response signal line ACK has become off, the [/0 device 5 retainsthe data line B1, and a seventh clock pulse is applied to thetranslating circuit 13. When the seventh pulse has been produced, thesecond, third and fourth gates 18, 19 and 20 are opened and at the sametime, the request signal ADRI is produced, and the data stored in theMAC register 10 are applied to the data line B2 through the third gate19. After that, when the response signal line SRVO becomes on, the MACregister 10 is set, and an eighth clock pulse is applied to thetranslating circuit 13.

Meanwhile, the data stored in the MAC register 10 and applied to theline B2 are also applied to an adder 15, and since a fifth gate 21 isopened, 1 is added to the data, and the added data are applied throughthe second gate 18 to the MAC register 10 to be stored therein. Afterthe eighth clock pulse was produced, when the response signal line SRVObecomes off, a ninth clock pulse is applied to the translating circuit13 and at the same time, 1" is added to the data stored in the TWRregister 14.

When the ninth clock pulse has been produced, the first gate 17 isopened and at the same time the request signal SRVI is produced, andwhen the response signal SRVO is produced, the IMR and FNR registers 9and 8 are set since the value in the TWR register 14 is 1, so that thedata on the data line B1 are applied through the first gate 17 to theIMR and FNR registers 9 and 8 so that the first four bits of the dataare stored in the FNR register 8, with the remaining 12 bits stored inthe [RM register 9, and a 10th clock pulse is applied to the translatingcircuit 13.

When the 10th clock pulse has been produced, the second and sixth gates18 and 22 are opened, but the fifth gate 21 is closed. After that, whenthe response signal line SRVO becomes off, the next clock pulse isapplied to the translating circuit 13 as equvalent to the seventh clockpulse, since the value in the TWR register 14 is l which is less than2". At this time, if the value in the TWR register 14 is 2," the TNRregister 11 is set, so that with the fifth gate being closed, the datastored in the TNR register 11 have l added thereto, and the result isagain stored in the TNR register 11. Thus, the operations from theseventh to the 10th clock pulses are repeated three times from the timewhen the fifth clock pulse was produced to reset the TWR register 14till the value in the TWR register 14 becomes 3. This will be explainedbelow in detail.

When the request signal REQD is produced and the response signal lineACK becomes on after the production of the fifth clock pulse, there arestored in a predetermined area of the processing unit 6 the first of theaddresses of the core memories of the unit 6 and the master controller 4in which the transferred data are to be stored, the instruction word andthe number of the words to be transferred. To put it in detail, theinstruction word is stored in the first four bits of the first of thepredetermined areas; the first address of the core memory of the mastercontroller 4 is stored in the remaining 12 bits thereof; the number ofthe words in the data to be transferred is stored in the second of theareas; and the first address of the core memory of the processing unit 6is stored in the third of the areas. Under the condition, when the ninthclock pulse has been produced, if the value in the TWR register 14 is 1"after the request signal SRVI is produced and the response signal SRVObecomes on, the instruction word and the first address of the mastercontroller 4 stored in the first of the predetermined areas of theprocessing unit 6 are applied to the data lines B1 and B3 so that theinstruction word and the first address of the master controller 4 arestored in the FNR and IMR registers 8 and 9, respectively. When thevalue in the TWR register 14 becomes 2, the number of the words to betransferred are supplied form the second of the predeterimined areas inthe processing unit 6 to the data lines B1 and B3 to be stored in theTNR register 11. When the value in the TWR register 14 becomes 3, thefirst address of the core memory of the processing unit 6 is suppliedfrom the third of the predetermined areas of the processing unit 6 tothe MAC register 10 to be stored therein. In this manner, theinstruction word stored in the FNR register 8 is read by the translatingcircuit 13 so that it is determined whether the instruction word is theinstruction to transfer the data in the processing unit 6 to the fixeddata of the master controller 4, or the instruction to transfer thedetected informations collected by the master controller 4 to theprocessing unit 6. Suppose that the instruction stored in the FNRregister 8 is to transfer the data in the processing unit 6 to theoperating time data in the master controller 4. Then, the lines MARC,RWGL and RWCL of the control lines C3 become on as will be describedlater.

When an 1 lth clock pulse has been produced, the re quest signal INTR isproduced. After that, when the response signal STRL is prduced, a 12thclock pulse is applied to the translating circuit 13. When the 12thclock pulse has been produced, the fourth, third and second gates 20, 19and 18 are opened and therequest signal ADRI is produced. Therefore, thedata stored in the MAC register 10 are applied to line B3 through thethird gate 19. When the response signal line SRVO becomes on, the MACregister 10 is set, so that the data in the MAC register 10 applied tothe line B2 are applied to the adder 15, where l is added to the dataand the resultant data are stored in the MAC register 10. Then, a 13thclock pulse is applied to the translating circuit 13.

When the 13th clock pulse has been produced, the seventh and eighthgates 23 and 24 are opened, so that the address of the memory device 100of the master controller 4 stored in the IMR register is applied to thedata line B4. When the response signal line SRVO becomes off," thecontrol line MARC becomes on, so that the data applied to the line B4are stored in the address register of the memory device 100 of themaster controller 4, and a 14th clock pulse is applied to thetranslating circuit 13.

When the 14th pulse has been produced, the first gate 17 is opened andthe request signal SRVI is produced. When the response signal SRVO isproduced, the BUR register 16 is set, so that the data applied to thedata line B1 are stored in the BUR register 16, and a l5th clock pulseis applied to the translating circuit 13.

When the 15th clock pulse is produced, the eighth and ninth gates 24 and25 are opened and the control lines RWCL and RWGL become on," so thatthe data stored in the BUR register 16 are applied to the data line B4and are written in the core memory whose address was designated when thel3th clock pulse was produced. After that, when the response signal SRVObecomes on, a 16th clock pulse is applied to the translating circuit 13.

When the sixteenth clock pulse has been produced, the six, fifth andsecond gates 22, 21 and 18 are opened and the TNR register 11 is set, sothat l is added to the data stored in the TNR register 11. After that, a17th pulse is applied to the translating circuit 13.

When the 17th clock pulse has been produced, the

seventh and second gates 23 and 18 are opened, and if the data stored inthe TNR register 11 are positive, the request signal ONEE is produced,while if the data are negative, the request signal ALLE is produced.When the response signal STPL becomes off, the IMR register 9 is set sothat 1 is added to the data stored in the IMR register and the resultantdata are again stored in the IMR register 9. Then, an 18th clock pulseis applied to the translating circuit 13.

When the 18th pulse has been produced, if the data in the TNR register11 are positive, the next clock pulse is applied to the translatingcircuit 13 as equivalent to the llth clock pulse, so that the operationsfrom the llth to 18th clock pulses are repeated. If the data in the TNRregister 11 are negative, however, the next clock pulse is applied tothe translating as equivalent to the first clock pulse so that theoperation of the system is completed. Thus, the data stored in the TNRregister 11 express the numberof the words of the data to betransferred, and every time the sixteenth pulse is applied to thetranslating circuit 13, l is added to the data, so that when thetransfer of all the data has been completed, the data in the TNRregister 11 become 0.

The case will now be described in which, after the production of thellth clock pulse, the instruction word stored in the FNR register 8 isto transfer the detected data in the memory of the master controller 4to the memory device of the processing unit 6.

When the 11th clock pulse has been produced, the request signal INTR isproduced. After that, when the response signal STPL becomes on," a 12thclock pulse is applied to the translating circuit 13. When the 12thclock pulse has been produced, the third, second and fourth gates 19, 18and 20 are opened, and the request signal ADRI is produced and therequest signal DRCT becomes on. After that, when the response signalSRVO becomes on, 1 is added to the data stored in the MAC register 10,and a 13th clock pulse is applied to the translating circuit 13. Whenthe 13th clock pulse has been produced, the seventh and eighth gates 23and 24 are opened, so that the data expressing the address of the corememory 100 of the master 4 stored in the [MR register 9 are applied tothe data line B4. After that, when the response signal SRVO disappears,the control line MARC is set so that the data on the line B4 are storedin the address register-of the'core memory 100 of the master controller4, and then a 14th clock pulse is applied to the translating circuit 13.When the 14th clock pulse has been produced, the tenth gate 26 is openedand the control lines MBRG and RWCL are set and the request signal READis produced. When the BUR register 16 is set, the data stored in theaddress of the core memory of the master controller 4 designated by the13th clock pulse are stored in the BUR register 16, and then a th clockpulse is applied to the translating circuit 13. When the 15th clockpulse has been produced, the ninth and fourth gates and 20 are areopened, and when reqiest signal SRVl is produced, the data in the BURregister 16 are applied to the data line B1. After that, when theresponse signal SRVO becomes on, a 16th clock pulse is applied to thetranslating circuit 13.

When the 16th pulse has been produced, the sixth, fifth and second gates22, 21 and 18 are opened, and the TNR register 11 is set, so that l isadded to the data in the TNR register 11. After that, a 17th clock pulseis applied to the translating circuit 13.

When the 17th clock pulse has been produced, the seventh and secondgates 23 and 18 are opened, and if the data stored in the TNR register11 are positive, the request signal ONEE is produced, whereas if thedata are negative, the request signal ALLE is prouced. When the responsesignal STPL becomes of the [MR register 9 is set, so that 1 is added tothe data in the lMR register 9. After that, an eighteenth clock pulse isapplied to the translating circuit 13.

When the 18th pulse has been produced, if the data stored in the TNRregister 11 are positive, the next clock pulse is applied to thetranslating circuit 13 as equivalent to the llth clock pulse, so thatthe operations from the 11th to 18th colck pulses will be repeated. Ifthe data in the TNR register are negative, however, the next clock pulseis applied to the translating circuit13 as the first clock pulse so thatthe operation of the system is completed.

In the above-mentioned operations of the master controller 4, thecollecting of the detected traffic information or data, the operation ofproviding control signals for the traffic signals, and the transfer ofthe data between the controller 4 and the processing unit 6 areconducted in the order mentioned.

Turning to FIG. 5, there are shown AND circuits 27, 28, 29 and to oneinput of which is applied the signal AK]. The signal AKI becomes on whenthe master controller 4 is to be operated, for example, when a timingpulse is produced for collection of the detected information, when atiming pulse is produced for operation of providing the control signals,or when a request for transfer of data between the master controller 4and the processing unit 6 is made. The other input signal to the ANDcircuit 27 becomes on" when a timing pulse for collection of thedetected traffic information is produced; the other input signal to theAND circuit 28 becomes on" when a timing pulse for operation ofproviding the control signals is produced; and the other input signal tothe AND circuit 29 becomes on when a request is made for transfer ofdata between the master controller 4 and the processing unit 6. Theoutput from each of the AND circuits 27, 28, 29 and 30 sets thecorresponding one of the four bits of a register 31 to render its output1, and when any one of the bits has been set, an OR circuit 32 producesan output signal to set a flip-flop 33.

The set output from the flip-flop 33 operates a counter IC1, while thereset output therefrom operates another counter 1C0. The latter counterlCO controls the collection of the detected traffic data and theoperation of providing control signals for the traffic signals in apredetermined order. The counter IC1 scans the outputs from the register31 after the signal AKI has been produced. If during the scanningoperation it detects any one of the outputs from the register 31, asignal CM is produced to reset the flip-flop 33.

Suppose that while the counter ICO is controlling a certain operation ofthe system, a timing pulse for collection of the detected trafficinformations coincides with the request for transfer of data between themaster controller 4 and the processing unit 6. At this time, the signalAKI must be l, so that the AND circuits 27 and 29 produce an output toset the first and third bits of the register 31. As a result, the outputsignal from the OR circuit 32 becomes 1 to set the flip-flop 33, so thatthe counter IC1 operates. This causes the reset output from theflip-flop 33 to become 0, so that the operation that has until then beenperformed by the counter [C0 is stopped. The counter 1C1 scans the firstto fourth outputs of the register 31. Since the first and third outputsare 1, the counter IC1 receives the first output to produce the outputCM to reset the flip-flop 33. Then, on the basis of the first output,the counter ICO controls the collecting operation of the detectedinformation. After the collecting operation has been finished, the datatransfer is yet to be conducted, so that the signal AKl is l Since thereis no timing pulse for the operation of providing control signals forthe traffic signals, the output from the third bit of the register 31 isscanned by the counter IC1 so that the transfer of data between theprocessing unit 6 and the master controller 4 is performed.

As previously mentioned, the master controller 4 performs the collectionof the detected traffic data, the operation of providing control signalsfor change of the traffic signals, and the transfer of data between thecontroller 4 and the processing unit 6 in the order mentioned. While thedata transfer is being conducted, if a timing pulse happens to beproduced for the collection of the detected data or for the operation ofproviding the control signals, the data transfer is temporarilyinterrupted. Also, while the operation of providing the control signalsis being performed, if a timing pulse is produced for the collection ofthe detected traffic informations, the operation is interrupted forcollection of the detected informations.

What we claim is:

1. An apparatus for centrally controlling traffic signals at differentlocations within a wide geographical area comprising:

a first control means for controlling the condition of traffic signals,including means for communicating between said first control means and aplurality of signal terminal stations, each of said signal terminalstations having at least one associated traffic signal, the terminalstations collecting traffic information and communicating said trafficinformation to said first control means, said first control meansfurther including means for storing data, said data being utilized bysaid first control means for controlling the condition of said trafficsignals, said data including operating time data for each of saidtraffic signals, an elapsed time, and traffic information received fromsaid traffic terminal stations, said first control means controlling thecondition of said traffic signals on the basis of said stored operatingtime data;

means for processing said traffic information received from said signalterminal stations, said processing means including means for updatingsaid operating time data stored in said storage means on the basis ofsaid processed traffic information;

a second control means connected to said first control means and saidprocessing means for controlling communication between said firstcontrol means and said processing means;

means connected to said first control means for generating timingsignals;

means included in said first control means and actuated by said timingmeans for comparing said elapsed time data with said operating timedata, and means actuated by said timing means for updating by one saidelapsed time data at predetermined intervals.

2. An apparatus according to claim 1, wherein said detected trafficinformation stored in said master controller are applied to saidprocessing unit every predetermined unit period of time, so that saidprocessing unit processes said operating time data.

3. An apparatus according to claim 2, wherein said processing meansincludes means for actuating said comparing means at the conclusion ofthe most recent updating of said operating time data stored in saidfirst control means by said processing means.

1. An apparatus for centrally controlling traffic signals at differentlocations within a wide geographical area comprising: a first controlmeans for controlling the condition of traffic signals, including meansfor communicating between said first control means and a plurality ofsignal terminal stations, each of said signal terminal stations havingat least one associated traffic signal, the terminal stations collectingtraffic information and communicating said traffic information to saidfirst control means, said first control means further including meansfor storing data, said data being utilized by said first control meansfor controlling the condition of said traffic signals, said dataincluding operating time data for each of said traffic signals, anelapsed time, and traffic information received from said trafficterminal stations, said first control means controlling the condition ofsaid traffic signals on the basis of said stored operating time data;means for processing said traffic information received from said signalterminal stations, said processing means including means for updatingsaid operating time data stored in said storage means on the basis ofsaid processed traffic information; a second control means connected tosaid first control means and said processing means for controllingcommunication between said first control means and said processingmeans; means connected to said first control means for generating timingsignals; means included in said first control means and actuated by saidtiming means for comparing said elapsed time data with said operatingtime data, and means actuated by said timing means for updating by onesaid elapsed time data at predetermined intervals.
 2. An apparatusaccording to claim 1, wherein said detected traffic information storedin said master controller are applied to said processing unit everypredetermined unit period of time, so that said processing unitprocesses said operating time data.
 3. An apparatus according to claim2, wherein said processing means includes means for actuating saidcomparing means at the conclusion of the most recent updating of saidoperating time data stored in said first control means by saidprocessing means.